Deposition apparatus have been widely used for manufacturing semiconductor devices such as photoresponsive devices, thin-film transistors, integrated circuits, device arrays, displays, and the like.
Thin film semiconductor materials offer several distinct advantages over crystalline wafer materials, insofar as they can be easily and economically fabricated into a variety of devices by mass production processes. Thin film semiconductor materials contemplated herein include amorphous, partially amorphous, and nanocrystalline. However, in the fabrication of thin film electronic devices such as photovoltaic devices, the presence of current-shunting, short circuit defects has been observed. These defects have (1) seriously impaired the performance of the electronic devices fabricated therefrom and (2) detrimentally affected production yield. These process-related defects are thought to either be present in the morphology of the substrate or back electrode; or develop during the deposition or subsequent processing of the intermediate semiconductor, dielectric or superconducting layers. Eliminating or at least substantially reducing the effects of these current-shunting defects has been the focus of much research.
The most important of these defects may be characterized as shunts, short-circuits, low resistance defect regions or low resistance current paths, such terms being employed interchangeably herein. Before the suspected causes of these defects are explained, it is helpful to note the typical thicknesses of the deposited intermediate layers. For example, in a p-i-n type electronic thin film device, a typical “p” layer may be only on the order of 250 angstroms thick, a typical “i” layer may be only on the order of 3,500 angstroms thick, and a typical “n” layer may be only on the order of 250 angstroms thick, thereby providing a total semiconductor body thickness of only about 4,000 angstroms. It should therefore be appreciated that irregularities, however, small, are not easy to cover by the deposited semiconductor layers.
Shunt defects are present when one or more low resistance current paths develop through the intermediate body of the device allowing current to pass unimpeded between the electrodes thereof. Under operating conditions, a photovoltaic device in which a shunt defect has developed, exhibits either (1) a low power output, since some of the electrical current collected at the electrodes flows through the defect region (the path of least resistance) in preference to an external load, or (2) complete failure where sufficient current is shunted through the defect region to “burn out” the device. Similarly, in thin film electronic resistive devices current is either shunted through the defect region resulting in severely degraded performance of the device, or the defect results in total, complete failure of the device.
While shunt-type defects always deleteriously affect the performance of electronic devices, their effect is particularly profound in photovoltaic devices which are operated under relatively low illumination, such as room light, vis-a-vis, high intensity illumination such as an AM-1 solar spectrum. Under room light illumination, the load resistance of the cell (i.e., the resistance under which the cell is designed to operate most efficiently) is comparable to the shunt resistance (i.e., the internal resistance imposed by the defect regions), whereas under AM-1 illumination, the load resistance is much lower by comparison. Furthermore, in a photovoltaic device, photogenerated current increases linearly with increasing illumination, while the resulting voltage increases logrithmically. In other words, voltage attains a relatively high value under low illumination, the value increasing only slightly as the intensity of the illumination is increased. The result is that under low illumination the relatively high voltage potential present preferentially drives the relatively small number of photogenerated current carriers through the path of least resistance, i.e., the low resistance defect regions. In contrast thereto, under high illumination, a large number of current carriers are present and are driven by a potential of about the same magnitude as the potential which exists under low illumination. This larger number of current carriers compete for a limited number of least resistance paths (through the defect regions). The result is that at high intensity, while more power may be lost to the defect region, the power lost is a smaller percentage of the total power produced than at low intensity illumination.
Defects or defect regions, the terms being interchangeably used herein, are not limited to “overt” or “patent” short circuit current paths. In some cases, the adverse effects of a defect are latent and do not immediately manifest themselves. Latent defects can give rise to what will be referred to hereinafter as an “operational mode failure”, wherein an electronic, or other semiconductor device, initially exhibiting satisfactory electrical performance, suddenly fails. This type of failure will be discussed in further detail hereinbelow. It is believed the shunt defects, both latent and patent, arise from one or more irregularities in the (1) morphology of the substrate material, (2) in the growth of the intermediate semiconductor layers or (3) unintended inclusions within the deposited layers.
The first, and perhaps most important, source of the defects, i.e., the aforementioned morphological irregularities in the deposition surface of the substrate material will now be discussed. Even though the highest quality sheet glass or stainless steel is employed to serve as the substrate upon which the conductive base electrode (either transparent oxide or metallic) upon which the intermediate semiconductor layers and the overlying metallic electrode are successively deposited, it has been calculated that from 10,000 to 100,000 irregularities per square centimeter are present on the deposition surface thereof. Such irregularities take the form of projections, craters, or other deviations from a smooth finish and may be under a micron in: 1) depth below the surface; 2) height above the surface; or 3) diameter. Regardless of their configuration or size, such defects may establish a low resistance current path through the intermediate semiconductor body, thereby effectively short-circuiting the two electrodes. This may occur in numerous ways. For instance, a spike projecting from the surface of the base electrode may be of too great a height to be covered by the subsequent deposition of semiconductor layers and therefore, be in direct electrical contact with the overlying metallic electrode when said electrode is deposited atop the intermediate semiconductor layers. Likewise, a crater formed in the surface of the substrate may be of too small a size to be filled by the subsequent deposition of the base electrode and semiconductor layers and therefore, be in sufficient proximity to the other electrode, when that electrode is deposited atop the semiconductor layers. In such an instance: 1) electrical current may bridge the gap which exists between the electrodes; or 2) during actual use of the electronic device, the material of one of the electrodes may, under the influence of the electrical field, migrate toward and contact the other of the electrodes, so as to pass electrical current therebetween and thereby give rise to an operational mode failure. It is also possible that in some cases the intermediate layers deposited onto the substrate or base electrode include regions of irregular composition which can provide low resistance paths for the flow of electrical current between the electrodes of the photovoltaic device.
Further, despite efforts to maintain a deposition vacuum envelope free of external contaminants, dust and other particulate matter may either invade the vacuum envelope during the deposition of the intermediate layer material, or forms as a by-product of the deposition process, which are deposited over the substrate electrode along with the semiconductor material. Such contaminants interfere with the uniform deposition of the intermediate layers and may establish low resistance current paths therethrough.
Additionally, it is suspected that in some cases, the intermediate materials form micro-craters or micro-projections during the deposition thereof, (even absent the presence of contaminants or external pollutants). Such morphological deviation from a perfectly smooth and even surface means that the substrate is covered by either: 1) an ultra-thin layer of material; or 2) not at all. Obviously, when the overlying metallic electrode material is deposited across the entire surface of the semiconductor body, the thin or open regions thereof create a low resistance current path. In still other cases, the presence of defect regions is only detectable by their deleterious effect upon the electrical and/or photoelectric properties of the resultant device.
In some instances, particular types of electronics devices may operate adequately in spite of the presence of such defects; however other devices, are significantly impaired in function by defects therein. While the defects described herein above may, in some instances, not be sufficiently severe to divert all electrical current through the low resistance path, the diversion or shunting of any current therethrough results in some loss in operational efficiency of the electronic device. Moreover, the shunting of even small amounts of current through each of thousands of defect regions will aggregate to cause major losses in efficiency. Based upon the foregoing, it should be apparent that a reduction in the number of defect regions is critical to the fabrication of high-yield, high efficiency, large area, thin film electronic devices.
Several approaches for dealing with this problem have been implemented in the past. As described in U.S. Pat. Nos. 4,451,970; 4,464,823; 4,510,674 and 4,510,675 of Masatsugu Izu and Vincent Cannella, the disclosures of which are incorporated herein by reference, the shunting of current through defect regions may be cured by substantially eliminating the defect regions as an operative area of the electronic device. This is accomplished in an electrolytic process wherein electrode material (in the preferred embodiment, indium tin oxide) is physically removed from the periphery of the defect site, effectively isolating the defect regions and preventing the flow of electrical current between the defect region and the electrode layer. As disclosed in U.S. Pat. No. 4,385,971 of Swartz, defect regions in a solar cell are electrolytically removed in a process which either etches, or bubble-blasts defective semiconductor regions from the solar cell, so as to physically remove material therefrom. However, in those instances where a current collecting structure such as a busbar system or a grid pattern is subsequently applied to the device, care must be taken in utilizing the aforedescribed processes so as to avoid having such conductive structure electrically contact the isolated defect, to avoid creating another short circuit. Consequently, insulating material is generally applied to the isolated regions. In U.S. Pat. No. 4,419,530 of Prem Nath, the disclosure of which is also incorporated herein by reference; there is described a method for electrically isolating defect containing small area segments of an amorphous, thin film, large area photovoltaic device. This isolation of defects is accomplished by: 1) dividing the large area device into a plurality of small area segments; 2) testing the small area segments for electrical operability; and 3) electrically connecting only those small area segments exhibiting a predetermined level of electrical operability, whereby a large area photovoltaic device comprising only electrically operative small area segments is formed.
While the method of Nath is effective in reducing or eliminating the effect of shunts, it is not completely satisfactory for several reasons. The step of dividing the semiconductor body into electrically isolated portions requires several production steps and also reduces the total area of the device. Further, the method can be time and cost intensive since the electrical output of each isolated portion must be individually tested and separate electrical connections must be made to provide electrical contact thereto. Also, since an entire segment is effectively eliminated from the final cell if it manifests a defect, losses of efficiency are greater than they would be if only the precise area of the particular defect were eliminated.
Further, U.S. Pat. No. 4,598,306 of Nath, et al., the disclosure of which is incorporated herein by reference, discloses the use of a resistive barrier layer interposed between the semiconductor body and one of the electrodes of a semiconductor device for limiting the amount of electrical current that can flow through defect regions. In this manner, the relatively large short circuit current flowing through defect regions is buffered by the current limiting resistance of the layer. While the foregoing method does improve the production yield of usable semiconductor devices, it interposes an additional series resistance therein, which resistance decreases the operational efficiency of the device.
Additionally, U.S. Pat. Nos. 4,590,317 and 4,633,033, the disclosures of which are incorporated herein, teach the use of various current collecting bus grid structures for the purpose of restricting short circuit current flow in semiconductor devices. According to the teachings therein, the current carrying capacity of grid systems of devices may be effectively restricted through the use of proper geometry, and/or materials. The limited current carrying capacity of such current collecting grids functions to buffer the effects of short circuit current flows through defect regions proximate thereto. While this system does significantly improve device yield, it obviously is of no use for semiconductor devices which do not include a current collecting grid structure therein; additionally, such grid structures, themselves, add some additional series resistance to the device.
Finally, U.S. Pat. Nos. 4,729,970 and 5,084,400, the disclosures of which are incorporated herein by reference, teach a methods of passivating short circuit defects in electronic devices having conductive electrodes. The '970 patent also teaches passivation of thin film electronic devices by employing either Lewis Acids or salts of amphoteric elements as the conversion reagents for passivation purposes. These disclosures teach passivation of current shunting circuit defects by altering the conductive oxide electrode or metallic electrode, proximate the defect regions.
In the past, techniques such as those disclosed in U.S. Pat. No. 4,729,970 ('970) have been sufficient to improve the yield of photovoltaic devices continuously deposited on elongated webs of stainless steel. However, as the instant assignee's technology for deposition of photovoltaic devices on elongated webs has advanced, the length of the webs on which the devices are deposited has become increasingly long. This means that the deposition chambers are in use longer between web changes and there is less down time. This is advantageous in that less down time means higher productivity and higher overall output for any give production machine. Unfortunately, a problem has developed. As the length of the web increases, the length of use of the deposition chambers also increases, and the chamber is purged/cleaned less often, resulting in an increased amount of particulate in the chamber. The inventors have discovered that in long runs, the low light voltage of VLL photovoltaic devices drops off after a certain point in the web, and continues to do so drastically, such that a significant portion of the tail end of the web is unusable for production of saleable photovoltaic devices. Thus, gains in productivity by using longer webs are undercut by losses in saleable yield. FIG. 1 graphs the VLL in millivolts versus the device number for two deposition runs. As can be seen from the run where the devices are passivated by the standard, prior art passivation technique (symbol ♦, 5V for 2 sec.), the higher device number (later in the deposition run) begin to have lower VLL until eventually at about device number 4500 or so, the VLL is below the acceptable limit of 900 mV.
While not wishing to be bound by theory, the instant inventors believe that the fall off of the low light voltage is due to a significant increase in the number of particles formed in the semiconductor deposition chamber (which eventually attach to and are incorporated into the device) as the length of the run is increased. This results in a higher number of shunt defects in the devices. Passivating the cells which have a larger density of shorting defects in the manner as described in the '970 patent results in decreased low light voltage. To increase the low light voltage, the defects must be more fully isolated. Toward this end, passivation processing time may be increased, but in so doing it has been found that a point is reached where a larger good area of the conductive electrode surrounding the defects is converted and changed in color, resulting in cosmetically unacceptable spots and a thinner top conducting oxide later. Thus there is a strong felt need in the art for a method of increasing the effectiveness of the passivation process to reduce the isolation loss of viable photovoltaic material while still properly passivating the short circuit shunts.